TUSB1210-Q1 data sheet, product information and support | TI.com
USB 2.0 Solutions | Arasan Chip Systems
USB 2.0 Full High Speed Solution | NXP Semiconductors
Standalone USB Transceiver Chip - EEWeb
USB 2.0 PHY for SoC Designs | Cadence IP
Archimago's Musings: MEASUREMENTS: Computer USB port noise, USB hubs and the 8kHz PHY Microframe Packet Noise
USB 2.0 PHY Verification
USB2 PHY | Cadence
HSIC USB 2.0 PHY IP
USB2.0 PHY – Silicon Library Inc.
USB 2.0 PHY IP Core Device Host OTG Hub in TSMC, 28HPC, 40LP /LL, UMC, 40LP, 28HPC, SMIC 14SF, SF, 55LL, 40LL - T2M-IP
USB2 Controller
USB 2.0 OTG IP Core | Arasan Chip Systems
Mixed-Signal Verification for USB 2.0 Physical Layer IP
Figure 4 from Verilog synthesis of USB 2.0 full-speed device PHY IP | Semantic Scholar
Figure 2 from Verilog synthesis of USB 2.0 full-speed device PHY IP | Semantic Scholar
DWTB: USB High Speed Inter-Chip (HSIC) IP: What is it? And why should I use it?
The USB 2.0 Device IP core | Arasan Chip Systems
High Speed Inter-CHIP USB 2.0 PHY | Arasan Chip Systems
Soft Mixed Signal Corporation USB 2.0 PHY IP Cores
USB2.0 Transceiver IC - USB3318 - COM-09631 - SparkFun Electronics
USB 2.0 PHY IP Device/Host/OTG/Hub (Silicon proven in TSMC 40LP /LL)
DWTB: USB High Speed Inter-Chip (HSIC) IP: What is it? And why should I use it?
